Running a Cycle-Accurate NES Emulator on ESP32 Microcontroller with Dual-Core FreeRTOS

1. Embedded Constraints: 520 KB SRAM

The Nintendo Entertainment System requires rendering $256 \times 240$ pixels at 60 FPS while synthesizing 5 audio channels and executing 6502 CPU instructions. On an embedded ESP32 microcontroller with constrained RAM, memory layout is paramount.

2. Dual-Core FreeRTOS Architecture

We decouple execution across both Xtensa LX6 cores using FreeRTOS task pinning: - Core 0: Executes the 6502 CPU cycle loop, cartridge mapper logic (NROM, MMC1, MMC3), and joypad polling. - Core 1: Drives the Picture Processing Unit (PPU) scanline renderer and streams pixel chunks to the ILI9341 display via hardware DMA over high-speed SPI (40 MHz).