- Modular C++ Architecture
- 8-Bit Tri-State Bus Model
- Microcode Instruction Logic
- Dear ImGui Real-Time Inspection
COMPUTER ARCHITECTURE / 8-BIT EMULATION
Simulating Computer Architecture from Silicon to Screen
BENCPU is a modular, binary-inspired CPU emulator written in C++ that models the fundamental hardware blocks of an 8-bit breadboard computer. Paired with a Dear ImGui desktop inspection frontend (CPUdockingimgui), it allows engineers to observe bus arbitration, clock cycles, and register state transitions in real time.
Central bus arbitration (my_Bus)
Models a tri-state data bus facilitating integer data transfers across components. Modules read and assert data onto the shared bus only when their respective output-enable control signals are active.
Programmable counter & sequencing
The program counter (my_counter) features clock edge sensitivity, synchronous load capabilities, and enable flags to step through memory addresses or branch conditionally.
Microcode control matrix & ALU
Coordinates timing pulses across fetch, decode, and execute stages. The ALU handles arithmetic and bitwise logic while updating zero and carry flags for branching.
Interactive desktop UI (CPUdockingimgui)
Built with GLFW and OpenGL3, the docking ImGui interface visualizes CPU registers (A, B, MAR, IREG, OUTREG), bus values, clock speeds, and memory tables with single-step execution controls.
Core Architectural Components
- Bus System
- Shared data pathway with updateBus() and getBusData() gating
- Program Counter
- Synchronous clock-driven counter with conditional load and enable
- Registers
- Accumulator (A), Operand (B), Memory Address (MAR), Instruction (IREG)
- ALU
- 8-bit adder/subtractor with Zero (Z) and Carry (C) status flags
- Visualizer
- Dear ImGui with docking panels, disassembly view, and memory explorer
- Language / Build
- C++14 / C++20 · CMake · MSBuild · Visual Studio
Educational & Systems Engineering Impact
The project combines low-level logic simulation with modern desktop tooling, offering a crystal-clear lens into how microcode instructions orchestrate hardware at the cycle level.